The present invention relates in general to power-on reset circuits, and more particularly, to a CMOS power-on reset circuit for providing an output signal during system start-up as the power supply voltage reaches a predetermined magnitude.
Power-on reset circuits are found in many applications wherein a delay is needed to provide time for the power supply voltage to ramp up to a sufficient operating level prior to the initialization of certain external circuitry. It is common to connect the output of the power-on reset circuit to the enable inputs of these external circuits to initially inhibit the operation thereof. In one example, the output signals of a clock distribution circuit are disabled at the system power-up until the power supply voltage reaches a sufficient level at which time the output clock signals are simultaneously enabled by the output signal of the power-on reset circuit to establish the correct phase relationship therebetween.
Conventional power-on reset circuits typically use a resistor and capacitor combination to introduce a time constant wherein some time is required to charge the capacitor to a predetermined voltage to trigger the output signal of the power-on reset circuit and thereby allow sufficient time for the power supply voltage to ramp up. In general, the time constant of the resistor and capacitor combination and the slew rate of the power supply voltage are not synchronized. A problem may occur if the slew rate of the power supply voltage is slow in comparison to the pre-established time constant permitting the output signal of the power-on reset circuit to enable the external circuitry before the power supply voltage reaches an operating level. Alternately, if the time constant is made extremely long, time is wasted after the power supply voltage reaches operating level until the time constant expires and the output signal of the power-on reset circuit changes state. Furthermore, conventional power-on reset circuits continue to consume power in static operation which is undesirable especially in CMOS technology.
Hence, there is a need for a power-on reset circuit operating independent of the slew rate of the power supply voltage and without a predetermined time constant to provide an output signal upon detecting a predetermined threshold of the power supply voltage start-up transient. In addition, the conduction paths through the power-on reset circuit are disabled during static operation for reducing the power consumption to substantially zero.